Reconfigurable microprocessors typically comprise a plurality of operational cells arranged in a grid, each operational cell being connectable to and disconnectable from other operational cells of the grid via a programmable interconnect. Data is processed by implementing a first set of reconfigurable signal processing paths comprising respective operational cells connected via the interconnect, processing the data along the first reconfigurable signal processing paths, implementing a second set of reconfigurable signal processing paths comprising respective operational cells connected via the interconnect, processing the data along the second reconfigurable signal processing paths and so on.
Routing circuitry is triggered to implement each subsequent set of reconfigurable signal processing paths by a global clock, even when the operational cells are asynchronous. Accordingly, there is typically a delay between the completion of signal processing (including settling time) by a given set of signal processing paths and the next clock cycle. Clock granularity is a factor affecting the average length of this delay. Over time, these delays accumulate and reduce the efficiency of the processor.
In addition, estimated signal propagation delays are relied upon to estimate when signal processing by a particular configuration will be complete. These signal propagation delays are typically “worst-case scenario” delays taking into account a range of environmental (e.g. temperature) conditions in which the processor is required to operate. This can lead to a delay of one or more clock cycles between completion of signal processing by the configuration and the clock cycle which triggers reconfiguration of the processor, again incurring unnecessary delays.
One way in which data processing speeds can be improved is to increase the clock speed. However, even if clock speed is increased, clock granularity would still be a factor affecting performance as there would still be a delay incurred between completion of signal processing and the next clock cycle. In addition, faster clocks are typically more expensive than slower clocks, and there are limits on how fast clocks can run. Furthermore, it would still be necessary to rely on estimated “worst-case scenario” signal processing delays before the processor can be reconfigured.
Accordingly, it would be advantageous to improve the way in which reconfigurable microprocessors operate in order to reduce these delays, so as to improve their efficiency and the speed at which they can process data.